//-----------------------------------------------------------------------------
//  Copyright (c) 2013 by HangZhou HenqgQiao Design Corporation. All rights reserved.
//
//  Project  : 
//  Module   : over sample the input data with 8-phases 311M clock
//  Parent   : 
//  Children : 
//
//  Description: 
//
//  Parameters:
//  Local Parameters:
//
//  Notes       : 
//
//  Multicycle and False Paths

module PTG_TOP(
    input                        CPU_RESETN,

    input                        SFI4_CLK200M_P,
    input                        SFI4_CLK200M_N,

    output[15:0]                 SFI4_0_TXDATA_P,
    output[15:0]                 SFI4_0_TXDATA_N,
    output                       SFI4_0_TXCLK_P,
    output                       SFI4_0_TXCLK_N,
    input                        SFI4_0_TXRFCLK_P,
    input                        SFI4_0_TXRFCLK_N,
    
    input[15:0]                  SFI4_0_RXDATA_P,
    input[15:0]                  SFI4_0_RXDATA_N,
    input                        SFI4_0_RXCLK_P,
    input                        SFI4_0_RXCLK_N,
    
    output[15:0]                 SFI4_1_TXDATA_P,
    output[15:0]                 SFI4_1_TXDATA_N,
    output                       SFI4_1_TXCLK_P,
    output                       SFI4_1_TXCLK_N,
    input                        SFI4_1_TXRFCLK_P,
    input                        SFI4_1_TXRFCLK_N,
    
    input[15:0]                  SFI4_1_RXDATA_P,
    input[15:0]                  SFI4_1_RXDATA_N,
    input                        SFI4_1_RXCLK_P,
    input                        SFI4_1_RXCLK_N,

    output[15:0]                 SFI4_2_TXDATA_P,
    output[15:0]                 SFI4_2_TXDATA_N,
    output                       SFI4_2_TXCLK_P,
    output                       SFI4_2_TXCLK_N,
    input                        SFI4_2_TXRFCLK_P,
    input                        SFI4_2_TXRFCLK_N,
    
    input[15:0]                  SFI4_2_RXDATA_P,
    input[15:0]                  SFI4_2_RXDATA_N,
    input                        SFI4_2_RXCLK_P,
    input                        SFI4_2_RXCLK_N,
    
    output[15:0]                 SFI4_3_TXDATA_P,
    output[15:0]                 SFI4_3_TXDATA_N,
    output                       SFI4_3_TXCLK_P,
    output                       SFI4_3_TXCLK_N,
    input                        SFI4_3_TXRFCLK_P,
    input                        SFI4_3_TXRFCLK_N,
    
    input[15:0]                  SFI4_3_RXDATA_P,
    input[15:0]                  SFI4_3_RXDATA_N,
    input                        SFI4_3_RXCLK_P,
    input                        SFI4_3_RXCLK_N
   );


wire         SFI4_0_RCLK, SFI4_1_RCLK, SFI4_2_RCLK, SFI4_3_RCLK;
wire[63:0]   SFI4_0_RDATA, SFI4_1_RDATA, SFI4_2_RDATA, SFI4_3_RDATA;
wire         SFI4_0_TCLK, SFI4_1_TCLK, SFI4_2_TCLK, SFI4_3_TCLK;
wire[63:0]   SFI4_0_TDATA, SFI4_1_TDATA, SFI4_2_TDATA, SFI4_3_TDATA;

  assign SFI4_0_TDATA[63:0]=SFI4_0_RDATA[63:0];
  assign SFI4_1_TDATA[63:0]=SFI4_1_RDATA[63:0];
  assign SFI4_2_TDATA[63:0]=SFI4_2_RDATA[63:0];
  assign SFI4_3_TDATA[63:0]=SFI4_3_RDATA[63:0];

SFI4_TOP                              INST_SFI4_TOP(
   .SFI4_RESET                        ( !CPU_RESETN ),

   .SFI4_CLK200M_P                    ( SFI4_CLK200M_P ),
   .SFI4_CLK200M_N                    ( SFI4_CLK200M_N ),

   .SFI4_0_TXDATA_P                   ( SFI4_0_TXDATA_P[15:0] ),
   .SFI4_0_TXDATA_N                   ( SFI4_0_TXDATA_N[15:0] ),
   .SFI4_0_TXCLK_P                    ( SFI4_0_TXCLK_P ),
   .SFI4_0_TXCLK_N                    ( SFI4_0_TXCLK_N ),
   .SFI4_0_TXRFCLK_P                  ( SFI4_0_TXRFCLK_P ),
   .SFI4_0_TXRFCLK_N                  ( SFI4_0_TXRFCLK_N ),
    
   .SFI4_0_RXDATA_P                   ( SFI4_0_RXDATA_P[15:0] ),
   .SFI4_0_RXDATA_N                   ( SFI4_0_RXDATA_N[15:0] ),
   .SFI4_0_RXCLK_P                    ( SFI4_0_RXCLK_P ),
   .SFI4_0_RXCLK_N                    ( SFI4_0_RXCLK_N ),
    
   .SFI4_0_RCLK                       ( SFI4_0_RCLK ),
   .SFI4_0_RDATA                      ( SFI4_0_RDATA[63:0] ),
   .SFI4_0_TCLK                       ( SFI4_0_TCLK ),
   .SFI4_0_TDATA                      ( SFI4_0_TDATA[63:0] ),



   .SFI4_1_TXDATA_P                   ( SFI4_1_TXDATA_P[15:0] ),
   .SFI4_1_TXDATA_N                   ( SFI4_1_TXDATA_N[15:0] ),
   .SFI4_1_TXCLK_P                    ( SFI4_1_TXCLK_P ),
   .SFI4_1_TXCLK_N                    ( SFI4_1_TXCLK_N ),
   .SFI4_1_TXRFCLK_P                  ( SFI4_1_TXRFCLK_P ),
   .SFI4_1_TXRFCLK_N                  ( SFI4_1_TXRFCLK_N ),
    
   .SFI4_1_RXDATA_P                   ( SFI4_1_RXDATA_P[15:0] ),
   .SFI4_1_RXDATA_N                   ( SFI4_1_RXDATA_N[15:0] ),
   .SFI4_1_RXCLK_P                    ( SFI4_1_RXCLK_P ),
   .SFI4_1_RXCLK_N                    ( SFI4_1_RXCLK_N ),
    
   .SFI4_1_RCLK                       ( SFI4_1_RCLK ),
   .SFI4_1_RDATA                      ( SFI4_1_RDATA[63:0] ),
   .SFI4_1_TCLK                       ( SFI4_1_TCLK ),
   .SFI4_1_TDATA                      ( SFI4_1_TDATA[63:0] ),

   .SFI4_2_TXDATA_P                   ( SFI4_2_TXDATA_P[15:0] ),
   .SFI4_2_TXDATA_N                   ( SFI4_2_TXDATA_N[15:0] ),
   .SFI4_2_TXCLK_P                    ( SFI4_2_TXCLK_P ),
   .SFI4_2_TXCLK_N                    ( SFI4_2_TXCLK_N ),
   .SFI4_2_TXRFCLK_P                  ( SFI4_2_TXRFCLK_P ),
   .SFI4_2_TXRFCLK_N                  ( SFI4_2_TXRFCLK_N ),
    
   .SFI4_2_RXDATA_P                   ( SFI4_2_RXDATA_P[15:0] ),
   .SFI4_2_RXDATA_N                   ( SFI4_2_RXDATA_N[15:0] ),
   .SFI4_2_RXCLK_P                    ( SFI4_2_RXCLK_P ),
   .SFI4_2_RXCLK_N                    ( SFI4_2_RXCLK_N ),
    
   .SFI4_2_RCLK                       ( SFI4_2_RCLK ),
   .SFI4_2_RDATA                      ( SFI4_2_RDATA[63:0] ),
   .SFI4_2_TCLK                       ( SFI4_2_TCLK ),
   .SFI4_2_TDATA                      ( SFI4_2_TDATA[63:0] ),



   .SFI4_3_TXDATA_P                   ( SFI4_3_TXDATA_P[15:0] ),
   .SFI4_3_TXDATA_N                   ( SFI4_3_TXDATA_N[15:0] ),
   .SFI4_3_TXCLK_P                    ( SFI4_3_TXCLK_P ),
   .SFI4_3_TXCLK_N                    ( SFI4_3_TXCLK_N ),
   .SFI4_3_TXRFCLK_P                  ( SFI4_3_TXRFCLK_P ),
   .SFI4_3_TXRFCLK_N                  ( SFI4_3_TXRFCLK_N ),
    
   .SFI4_3_RXDATA_P                   ( SFI4_3_RXDATA_P[15:0] ),
   .SFI4_3_RXDATA_N                   ( SFI4_3_RXDATA_N[15:0] ),
   .SFI4_3_RXCLK_P                    ( SFI4_3_RXCLK_P ),
   .SFI4_3_RXCLK_N                    ( SFI4_3_RXCLK_N ),
    
   .SFI4_3_RCLK                       ( SFI4_3_RCLK ),
   .SFI4_3_RDATA                      ( SFI4_3_RDATA[63:0] ),
   .SFI4_3_TCLK                       ( SFI4_3_TCLK ),
   .SFI4_3_TDATA                      ( SFI4_3_TDATA[63:0] )

    );
endmodule


